Silica (SiO2) films formed by vacuum processes such as CVD method have hitherto been often adopted as interlayer dielectrics in semiconductor elements and the like. Further, SOG (spin-on-glass) films, which are wet-coating type insulating films principally made of tetraalkoxysilane hydrolysate, are also employed mainly for the purpose of leveling. Recently, according as semiconductor elements and like have been getting more integrated, demands to interlayer dielectrics of low permittivity have increasingly grown in expectation of reducing stray capacity among the wirings and thereby of improving wire delay. As a means for reducing stray capacity among the wirings, semiconductor devices disclosed in Patent documents 1, 2 and 3 contain gaps formed among the wirings. Those documents disclose a method comprising the steps of: filling gaps among the wirings with a filler, such as, organic resist or silica compound; and then removing the filler by etching or ashing to form gaps among the wirings. However, that method needs complicated operations, and hence there is room for improvement. Further, although Patent documents 4, 5 and 6 disclose fillers for forming gaps among the wirings, those fillers are poor in thermal stability at about 400° C. and hence cannot fully reduce stray capacity among the wirings. Accordingly, there is also room for improvement.